1. Field of the Invention
The present invention generally relates to nonvolatile memories. More specifically, the present invention provides a novel structure of nonvolatile memory and a method of manufacturing the same.
2. Description of the Related Art
Nonvolatile memory is a kind of memory device in which the stored data is not lost when powered off. There are several nonvolatile memory cell using semiconductors such as flash and electrically erasable programmable read-only memory (EEPRON) etc. In recent years, the market for nonvolatile memory has grown rapidly as a result of the need for mobile phones and network communication etc.
There are several popular nonvolatile memory cell structures. The first nonvolatile memory cell is the so-called stacked gate nonvolatile cell, as depicted in FIG. 1 (Prior Art). In FIG. 1, numeral 1 represents a p type silicon substrate. Numeral 2 represents a tunneling dielectric layer formed on the silicon substrate generally consisting of a SiO2 layer, while SiON, Si3N4, HfO2 or ZrO2 can also be employed. Numeral 3 represents a floating gate (FG) formed on the tunneling dielectric layer generally consisting of polysilicon. Numeral 4 represents a dielectric layer formed on the floating gate generally consisting of SiO2, ONO, SiON, Si3N4, HfO2 or ZrO2. Numeral 5 represents a control gate (CG) formed on the dielectric layer. A capping dielectric layer 6 may be formed on the upper portion of the control gate (CG) 5 according to the demand. Each sidewall of the stacked gate has a spacer 7 generally consisting of an oxide or nitride. One side of the stacked gate has an n doped source region 8 and another side has an n doped drain region 9. In erasing, the stacked gate nonvolatile cell can be erased by F-N tunneling effect through the source region 8, the drain region 9 or the silicon substrate 1 to release electrons trapped in the floating gate 3.
Another conventional cell structure, referred to as the split gate memory cell, as shown in FIG. 2 (Prior Art). In FIG. 2, numeral 11 represents a p type silicon substrate. Numeral 12 represents a tunneling dielectric layer formed on the silicon substrate. Numeral 13 represents a floating gate (FG) formed on the tunneling dielectric layer generally consisting of polysilicon. Numeral 14 represents a dielectric layer formed on the floating gate generally consisting of an ONO. Numeral 15 represents a control gate (CG) formed on the dielectric layer. One portion of the control gate 15 is located over the floating gate 13, while another portion of the control gate 15 is extended on the silicon substrate 11, the tunneling dielectric layer 12 and the dielectric layer 14. One side of the split gate has an n doped source region 18 and another side has an n doped drain region 19. In erasing, the split gate nonvolatile cell can be erased by F-N tunneling effect through the drain region 19 or the silicon substrate 11 to release electrons trapped in the floating gate 13. Alternately, positive voltage is applied to the control gate 15 thus the electron trapped in the floating gate 13 is released.
In programming, a scheme of so-called channel hot-carrier injection is usually employed by the above conventional stacked gate and split gate memory cells. In detail, the source region is grounded, positive voltage is applied to the drain region and the gate, and therefore the hot carriers inject into the floating gate through the channel adjacent to the drain region. However, this programming procedure has a main disadvantage, hot carrier creation inefficiency, therefore a higher voltage is needed to abbreviate the programming time.
Ken Uchida et al. disclosed a new scheme of hot-carrier injection in Applied Physics Letters (76 (27), p. 3992, Jun. 21, 2000). A metal silicide is employed as a source region of a device and connects with a channel region to form a Schottky barrier. As demonstrated by the experiments, hot carriers can inject into a gate through the channel region adjacent to the source region. This scheme is more efficient then conventional schemes, therefore the programming voltage can be lower. However, this structure has an essential disadvantage when applied in nonvolatile memory unit. Since the source region is a metal silicide, a reading current is limited by the Schottky barrier resulting in shrinkage when reading. Otherwise, if a drain region is a metal silicide, a huge junction leakage will occur when operating.
Therefore, an object according to the present invention is to provide a novel structure of nonvolatile memory and a method of manufacturing the same with a metallic source to achieve source-side hot electron injection to solve the above-mentioned problems of the programming of conventional structures. Another object according to the present invention is to create a Schottky contact formed only at a contact of the metallic source and the channel of a device, then a highly n doped region is formed at a contact of a lower portion of the metallic source and a p type substrate and at a drain junction of a drain and the p type substrate, respectively, thereby further improving the reading current of the cell and avoiding large junction leakage.
The present invention achieves the above-indicated objects by providing a novel structure of nonvolatile memory that is formed on p type silicon. This memory cell includes a stacked gate a tunneling dielectric layer, a floating gate (FG), a dielectric layer and a control gate (CG). One side of the stacked gate has a source region and another side has an drain region, wherein the surface of the source region includes a thin metal silicide connecting with a channel region to form a Schottky barrier. A tilted angle implant with As or P doping is performed on the p type silicon substrate to form a drain region and extend a portion of the drain region to a channel region under the stacked gate. In implanting, an n doped source region is also formed by some dosage, creating an offset between the source region and the channel region as a result of the tilted angle implant. In programming, the source region is grounded, positive voltage is applied to the drain region and the gate, therefore, the hot carriers inject into the floating gate through the channel adjacent to the source region.
The present invention also provides another novel structure of nonvolatile memory that is made on p type silicon. This memory cell includes a split gate a tunneling dielectric layer, a floating gate (FG), a dielectric layer and a control gate (CG). One side of the split gate has a source region and another side has an drain region, wherein the surface of the source region includes a thin metal silicide connecting with a channel region to form a Schottky barrier. A tilted angle implant with As or P doping is performed on the p type silicon substrate to form an drain region and extend a portion of the drain region to a channel region under the split gate. In implanting, an n doped source region is also formed by some dosage, creating an offset between the source region and the channel region as a result of the tilted angle implant. In programming, the source region is grounded, positive voltage is applied to the drain region and the gate, and therefore the hot carriers inject into the floating gate through the channel adjacent to the source region.